1. Field of the Invention
The present invention relates generally to the field of circuit boards. More particularly, the present invention relates to a method for manufacturing a packaging substrate. Two selective etching steps are utilized to define the Au-plating area and the non-Au-plating area.
2. Description of the Prior Art
As the functionality and performance of network systems, high-end servers, and mobile communication devices improves, the demand for high-performance, high pin count packages is increasing. This increasing demand requires new technologies, which incorporate high pin count and also delivers performance via impedance control, low crosstalk, DC/AC resistance, and low VG impedance. Sophisticated interconnect technology has become essential for meeting these needs by improving the density and reliability of the substrates for LSI package and module boards. While high-density packages such as flip-chip and BGA devices permit very high input-output (I/O) counts, the resulting close dimensions introduce substantial yield and cost challenges.
As known in the art, dense circuit patterns with intensive fine copper lines that are electrically connected to a number of contact pads are fabricated on the surface of the packaging substrate for the transmission of electronic signals or power. On the top surface of the electrical contact pads, a Ni/Au layer, which is also referred to as “soft gold layer”, is typically formed with electroplating to ensure that the bonding pads are in excellent electrical coupling with a circuit of a chip. Furthermore, other electrical contact pads of a substrate, solder ball pads for example, are covered with a Ni/Au layer electroplated on the surface, so that the conducting pads (usually made of copper composition) of the solder ball pads can be prevented from oxidation to improve the electrical interconnection performance of the solder ball pads. After the Ni/Au layer plating, surface finish processes such as solder mask coating are then carried out to finish the manufacturing of the packaging substrate.
To fabricate a packaging structure, in accordance with some prior art methods in the public domain, it is required to dispose a plurality of conducting wires for electroplating. These conducting wires are also known as “plating bus”, which are used to assist the electroplating process for forming the Ni/Au structure electroplated on the contact pads. However, These conducting wires occupy a large amount of area, thus leading to sacrificing the surface area for functional circuit layout pattern. Another drawback of employing plating bus is that when operating at high frequency, noise due to the antenna effect may occur, and thus adversely affecting chip performance.
U.S. Pat. No. 6,576,540 filed Mar. 22, 2002, entitled “Method for fabricating substrate within a Ni/Au structure electroplated on electrical contact pads”, teaches a method comprising the steps of: providing a substrate with a circuit layout pattern and forming a conducting film on the surface of the substrate; depositing a first photoresist layer within an opening on said electrical conducting film surface to expose a portion of said circuit layout pattern to be electrical contact pads; removing the exposed conducting film uncovered by the first photoresist layer; depositing a second photoresist layer, covering the conducting film exposed in the openings of the first photoresist layer; electroplating Ni/Au covering the surface of the electrical contact pads; removing the first and second photoresists, and the conducting film covered by the photoresists; depositing solder mask on the substrate within an opening to expose said electrical contact pads.
The method disclosed in U.S. Pat. No. 6,576,540 has several shortcomings. First, the process is costly because an additional metallization is needed after the patterning of circuit lines on the substrate. In addition, the fine conductive lines on the substrate might be unwarily scratched or damaged due to collision. Furthermore, metal peeling problem is also an issue that potentially affecting the production yield.
Taiwanese Pat. Pub. No. 538,512, which is incorporated herein by reference, teaches a process for making packaging substrate by utilizing stacked photoresist image transfer layers. However, the process disclosed in this patent has a Ni/Au overhang problem due to that the sidewalls of the contact pad are not covered by the Ni/Au layer. The exposed sidewalls of the contact pads may be oxidized resulting in short circuiting or reliability concerns.
In light of the above, there is a strong need in the packaging industry to provide a cost-effective method for manufacturing a packaging substrate to solve the above-described problems.